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Clock Lines

The changes of state of all bused signals are synchronized to one or more clock signals, which are distributed to all functional units on the bus.

Read and write operations between the CPU and memory units are the most common. One approach is for the CPU to set the address lines and data lines and then blindly issue the control pulses, assuming that the slave unit will respond as needed within the allowed time. A more elegant but slightly slower technique uses a handshake which requires an acknowledgment response from the slave before proceeding.

Doug Gingrich
Tue Jul 13 16:55:15 EDT 1999