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SFR explanation for PIC16F877(4)

ADCON0 ( A/D converter control register 0 ) 1Fh The A/D converter condition is controlled with this register. The value in the parenthesis is in the condition immediately after the turning on. ADCS1,ADCS0 : A/D conversion clock select bits ADCS1 ADCS0 Clock 0 0 Fosc/2 0 1 Fosc/8 1 0 Fosc/32 1 1 RC In case of RC, the clock is driven from an RC oscillator. CHS2,CHS1,CHS0 : Analog channel select bits CHS2 CHS1 CHS0 Input channel 0 0 0 Channel 0 ( RA0/AN0 ) 0 0 1 Channel 1 ( RA1/AN1 ) 0 1 0 Channel 2 ( RA2/AN2 ) 0 1 1 Channel 3 ( RA3/AN3 ) 1 0 0 Channel 4 ( RA5/AN4 ) 1 0 1 Channel 5 ( RE0/AN5 ) 1 1 0 Channel 6 ( RE1/AN6 ) 1 1 1 Channel 7 ( RE2/AN7 ) GO/DONE : A/D conversion status bit 1 : A/D conversion in progress 0 : A/D conversion not in progress ( This bit is automatically cleared by hardware ) ADON : A/D ON bit 1 : A/D conversion module is operating 0 : A/D conversion module is shutoff and operating current ADCON1 ( A/D converter control register 1 ) 9Fh The A/D converter condition is controlled with this register. The value in the parenthesis is in the condition immediately after the turning on. ADFM : A/D result format select 1 : Right justified. 6 most significant bits of ADRESH are read as 0. 0 : Left justified. 6 least significant bits of ADRESL are read as 0. PCFG3,PCFG2,PCFG1,PCFG0 : A/D port configuration control bits PCFG 3210 Port Remarks AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 0000 A A A A A A A A 0001 A A A A VREF+ A A A 0010 D D D A A A A A 0011 D D D A VREF+ A A A 0100 D D D D A D A A 0101 D D D D VREF+ D A A 0110 D D D D D D D D Same as 0111 0111 D D D D D D D D Same as 0110 1000 A A A A VREF+ VREF- A A 1001 D D A A A A A A 1010 D D A A VREF+ A A A 1011 D D A A VREF+ VREF- A A 1100 D D D A VREF+ VREF- A A 1101 D D D D VREF+ VREF- A A 1110 D D D D D D D A 1111 D D D D VREF+ VREF- D A A: Analog port D: Digital port VREF+: High reference voltage VREF-: Low reference voltage GPR ( General Purpose Register ) 20h-7Fh/A0h-FFh/110h-17Fh/190h-1FFh The general purpose register has the area which is common to all the banks and an area of each bank. The area of each bank can not do reading and writing when it doesn't change a bank. The composition of the area is different from PIC16F873. Kind Capacity Address Common of all the banks 16 bytes 70h-7Fh ( F0h-FFh ) ( 170h-17Fh ) ( 1F0h-1FFh ) Each bank Bank0 80 bytes 20h-6Fh Bank1 80 bytes A0h-EFh Bank2 96 bytes 110h-16Fh Bank3 96 bytes 190h-1EFh