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'[EE] Re: capacitor ripple current'
2005\08\14@131019 by Martin Klingensmith

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That would be interesting to see.
It's a 3 phase BLDC control. I calculated about 10A ripple absolute max
with a spice simulation. I'm not sure how accurate my model is but I
don't think it's far off. With two capacitors per phase and a PWM of
50kHz and a maximum speed of around 5k RPM the capacitors will only see
the max current for ten PWM periods once every 100uS.

The RMS current would be max/sqrt(2) which is about 7A. Split between
two capacitors results in 3.5A ripple. I don't know how good my math is
there so I will try to do some more signal analysis but I think I'm close.

David Van Horn wrote:

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--
Martin Klingensmith
http://wwia.org/
http://nnytech.net/

2005\08\15@001145 by Chen Xiao Fan

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For this kind of system simulation, PSIM is one of the best
tools. Still the demo version can only simulate small design.
I've seen some experts simulate the whole converter (5kW three
phase PFC/APF with one-cycle control) using PSIM. Generally
speaking PSpice is doing a bad job to get converged. I was
told by him that it is easy to build the converter than to
simulate it in PSpice.  :) And it is actually several months
work to build the converter. Maybe it is just his opinion.
SABER is better but is too expensive.

As for the capacitor loss, I think the major loss will be the
ESR loss. Just note that the ESR data on the datasheet can not
really be trusted. There are some other loss as well.

Regards,
Xiaofan

{Original Message removed}

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