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'[PIC]: Re: PWM on 16C712'
2000\08\07@145058 by Olin Lathrop

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First, do try to remember the [PIC]: in the subject line.  I almost didn't
notice this, and I would have gotten a "reminder" from a list admin.  (Yes,
they send these even to people who only pass on the problem by replying).

> Period = (PR2+1)*4*Tosc*Prescale
> The shortest period attainable is therefore 0.4uS (T0sc = 0.1uS, Prescale
= 1)
> However, the resolution available at this period is not workable (1 bit!)
> The value in DC1 controls the duty cycle, but I cannot use a wider word
> than that in PR2.

No, there are an additional 2 bits available.  These are set in CCP1CON
<5:4>.

> IOW if PR2 is 00001110 then I can only use up to 00001111 in DC1, limiting
> the PWM resolution to 4 bits.
> To get 6 bit resolution, I have to use at least 3E (00111110) in PR2, so
> the period drops to 102uS

Timer 2 has two additional "fraction" bits that are used to compare to the
CCP1CON<5:4> bits.  These two fraction bits either come from the low 2 bits
of the prescaler or the Q1-Q4 clock phases.  Check out the "PWM mode"
section of the data sheet.  This is all described quite nicely.


*****************************************************************
Olin Lathrop, embedded systems consultant in Devens Massachusetts
(978) 772-3129, spam_OUTolinTakeThisOuTspamcognivis.com, http://www.cognivis.com

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2000\08\07@152627 by David VanHorn

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I see what I missed now, the period is calculated from Fosc/4 and the
on-time is calculated from Fosc, allowing two more bits of resolution.  I
kept thinking I had the definitions reversed somehow, because Ton couldn't
logically exceed the period.
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