According to the July press release,
"Prices range from $6.16 each for the PIC18C242
to $7.41 each for the PIC18C452, all in
10,000-unit quantities. Samples are planned
for August, with volume shipments expected in
the third quarter. The MPLAB-C18 C compiler is
expected to be available in August for $495."
By my calander, 3Q99 is winding down... mostly just
September to go. Any sightings?
Bob Drzyzgula It's not a problem
drzyzgula.org until something bad happens bob
On Fri, 27 Aug 1999, Bob Drzyzgula wrote:
> According to the July press release,
> "Prices range from $6.16 each for the PIC18C242
> to $7.41 each for the PIC18C452, all in
> 10,000-unit quantities. Samples are planned
> for August, with volume shipments expected in
> the third quarter. The MPLAB-C18 C compiler is
> expected to be available in August for $495."
> By my calander, 3Q99 is winding down... mostly just
> September to go. Any sightings?
I'm curious too. gpasm and gpsim are going to be released very soon with
support for the 18cxx2 core.
If you get a chance you really oughta download the new data sheet and read
about this puppy. It's quite impressive. While developing gpsim I've come
across some really neat things you can do with the new instruction set.
BTW, in case anyone from microchip is monitoring this thread, I've got a
couple of questions about the 18cxx2 core:
1) Do the rotate instructions REALLY affect the Z-bit?
2) What happens when an indirect register is accessed indirectly?
fsr0h:fsr0l = &indf1
fsr1h:fsr1l = &some_register
I have just read the (preliminary) data sheet for the
new PIC18CXXX chip, which I find very impressive.
If the price is right this will definitely be included
in some of my future designs.
Now to my question - The chip has instructions for table
read and table write of the program memory. Table read
I understand (lookup tables, ROM checksum ...), but not
the table write. Is it possible to write to the program
memory during program execution? As I understand it, the
chip is based on EPROM, which in a plastic package is OTP.
If it would have been EEPROM or FLASH it would have been
great (a lot of non volatile memory on chip).
Is this for programming the chip or a feature which will
be usable first when there is FLASH or EEPROM versions
AB Liros Elektronik
Box 9124, 200 39 Malmv, Sweden
TEL INT +4640142078
FAX INT +4640947388
On Thu, 2 Sep 1999, [ISO-8859-1] Ruben Jönsson wrote:
> I have just read the (preliminary) data sheet for the
> new PIC18CXXX chip, which I find very impressive.
> If the price is right this will definitely be included
> in some of my future designs.
Exactly my feelings too.
According to section 5.1.1, the section about the RCON register, the
TBLWRT is applicable when Vpp is applied to the /MCLR pin.
Now my turn.
How do you think this instruction will execute?:
Scott Dattalo wrote:
> Now my turn.
> How do you think this instruction will execute?:
> movff postdec0,preinc0
I haven't tried it because my 18Cxxx Engineering Sample is still under
the swings in Microchip's backyard sand box, but I would assume the data
is placed back into the same location.
read from 55h, dec = 54h
inc = 55h, save to 55h
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