I ran into something similar doing I2C i/o between a 756 (I2C master) and a
63 (I2C slave), using the built-in I2C. The 63 was asleep waiting for an
I2C start condition to wake it from sleep. The problem is the time it takes
the oscillator to come up, it takes a millisecond or two. We got round it
by sending an I2C start (from the 756) and then waiting a few ms before
sending the data. The 63 then had time to wake up. If we didn't do this:
1. The START wakes the 63. The oscillator starts to come up.
2. While waking, the 63 hardware receives the first byte: the I2C hardware
runs nicely while the chip is alseep/without oscillator.
3. The second byte comes in, before the oscillator has stabilized and before
the IRQ code can read the buffered byte. Overrun!
Maybe you could have an extra line. Let's say a 'wake up' line to B0 and
then a data line to another non-IRQ port.
B0 wakes you up, you monitor the second port for a start condition. The
sender raises the wake up line, waits a bit and then sends the data on the
second line, clearing the wake up line at some suitable time during or at
the end of the send.
You could use a single line if you send an on/off pulse and then wait before
sending the data.
VP of Engineering
I have the same problem in my system, where PICS are I2C slaves
and wake when addressed on I2C. I just accept the fact that the
first write to the slave better have no payload, and consider it a wake-
up call. If I needed to send data in that first message, I'd consider
Start, Address, (wait with clock stopped low), data.... , Stop
which would prevent overruns.
Also, If you do get the overrun, is that so bad? The SSP NACKs
and gets off the bus, and the Master can detect the failure and re-
try. That would allow you to use the same messages and logic in the
Master, whether the Slave was awake (and got it the first time) or
was asleep (and missed the first message).
Barry King, KA1NLH
NRG Systems "Measuring the Wind's Energy"
Hinesburg, Vermont, USA
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