'timer1 on 16c65'
David E. Queen
I plan on using an interrupt on timer 1 overflow to do some timing.
If the ISR always takes the same number of clock cycles, something I am
working on with MPLAB,
will .1% or better timing accuracy be a reasonable goal? from what I have
read so far,
and I have not read all 300 pages yet, I should set the timer to
2^16-50,000-cycles in ISR)
timer one counts the PIC oscillator (20mhz/4 = 5,000,000 counts per second)
interrupt every 1ms
maximum time 10 seconds (10,000 interrupts)
all I need to do in the ISR, not counting the ISR service
inc a 16 bit number
compare 3 16 bit numbers to the above number
clear an IO pin as each compare is true
> From: "David E. Queen" <NNL.NET> dqueen
> I plan on using an interrupt on timer 1 overflow to do some timing.
> If the ISR always takes the same number of clock cycles, something I am
> working on with MPLAB,
> will .1% or better timing accuracy be a reasonable goal? from what I have
> read so far,
> and I have not read all 300 pages yet, I should set the timer to
> 2^16-50,000-cycles in ISR)
You can achieve accuracy limited only by your XTAL. Unless there is
something particularly magic about 1ms, perhaps use a more 'natural'
interval such as Fosc/(4*256*256) etc.
From my experience, the PIC series have a fairly consistent interrupt
latency - make that very consistent if you are using timers synchronised
to the system clock as opposed to external, asynchronous, events.
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